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CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F
18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM
Features
* Supports bus operation up to 250 MHz * Available speed grades are 250, 200, and 167 MHz * Registered inputs and outputs for pipelined operation * Optimal for performance (double-cycle deselect) * Depth expansion without wait state * 3.3V core power supply (VDD) * 2.5V or 3.3V IO power supply (VDDQ) * Fast clock-to-output times -- 2.6 ns (for 250 MHz device) * Provides high-performance 3-1-1-1 access rate * User selectable burst counter supporting interleaved or linear burst sequences * Synchronous self timed writes * Asynchronous output enable * CY7C1386D/CY7C1387D available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non Pb-free 165-ball FBGA package. CY7C1386F/CY7C1387F available in Pb-free and non Pb-free 119-ball BGA package * IEEE 1149.1 JTAG-Compatible Boundary Scan * ZZ sleep mode option Intel(R) Pentium(R)
Functional Description [1]
The CY7C1386D/CY7C1387D/CY7C1386F/CY7C1387F SRAM integrates 512K x 36/1M x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive edge triggered clock input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (CE1), depth expansion chip enables (CE2 and CE3 [2]), burst control inputs (ADSC, ADSP, and ADV), write enables (BWX, and BWE), and global write (GW). Asynchronous inputs include the output enable (OE) and the ZZ pin. Addresses and chip enables are registered at rising edge of clock when either address strobe processor (ADSP) or address strobe controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the advance pin (ADV). Address, data inputs, and write controls are registered on-chip to initiate a self timed write cycle.This part supports byte write operations (see Pin Configurations on page 3 and Truth Table [4, 5, 6, 7, 8] on page 9 for further details). Write cycles can be one to four bytes wide as controlled by the byte write control inputs. GW active LOW causes all bytes to be written. This device incorporates an additional pipelined enable register which delays turning off the output buffers an additional cycle when a deselect is executed.This feature allows depth expansion without penalizing system performance. The CY7C1386D/CY7C1387D/CY7C1386F/CY7C1387F operates from a +3.3V core power supply while all outputs operate with a +3.3V or +2.5V supply. All inputs and outputs are JEDEC-standard and JESD8-5-compatible.
* Separate processor and controller address strobes
Selection Guide
250 MHz Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 2.6 350 70 200 MHz 3.0 300 70 167 MHz 3.4 275 70 Unit ns mA mA
Notes 1. For best practices or recommendations, please refer to the Cypress application note AN1064, SRAM System Design Guidelines on www.cypress.com. 2. CE3 and CE2 are for TQFP and 165 FBGA packages only. 119 BGA is offered only in Single Chip Enable.
Cypress Semiconductor Corporation Document Number: 38-05545 Rev. *E
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised Feburary 09, 2007
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CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F
Logic Block Diagram - CY7C1386D/CY7C1386F [3] (512K x 36)
A0,A1,A
ADDRESS REGISTER
2 A[1:0]
MODE ADV CLK
BURST LOGIC
Q1
COUNTER AND
CLR ADSC ADSP BW D DQ D, DQP D BYTE WRITE REGISTER DQ c,DQP C BYTE WRITE REGISTER DQ B ,DQP B BYTE WRITE REGISTER DQ A, DQP A BYTE WRITE REGISTER ENABLE REGISTER
Q0
DQ D, DQP D BYTE WRITE DRIVER DQ c,DQP C BYTE WRITE DRIVER DQ B ,DQP B BYTE WRITE DRIVER DQ A, DQP A BYTE WRITE DRIVER
MEMORY ARRAY SENSE AMPS
BW C
OUTPUT REGISTERS
OUTPUT BUFFERS
E
BW B
DQs DQP A DQP B DQP C DQP D
BW A BWE GW CE 1 CE 2 CE 3 OE
PIPELINED ENABLE
INPUT REGISTERS
ZZ
CONTROL
Logic Block Diagram - CY7C1387D/CY7C1387F [3] (1M x 18)
A0, A1, A
ADDRESS REGISTER 2 A[1:0]
MODE ADV CLK
Q1 BURST COUNTER AND
CLR Q0
ADSC ADSP DQ B, DQP B BYTE WRITE REGISTER DQ A , DQP BYTE WRITE REGISTER ENABLE REGISTER DQ B , DQP B BYTE MEMORY ARRAY SENSE AMPS
BW B
OUTPUT REGISTERS
OUTPUT BUFFERS E
DQ A, DQP A BYTE
DQs, DQP A DQP B
BW A BWE CE 1 CE 2 CE 3 OE
PIPELINED ENABLE
INPUT REGISTERS
SLEEP CONTROL
Note 3. CY7C1386F and CY7C1387F have only 1 Chip Enable (CE1).
Document Number: 38-05545 Rev. *E
Page 2 of 30
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CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F
Pin Configurations 100-pin TQFP Pinout (3 Chip Enables)
A A CE1 CE2 BWD BWC BWB BWA CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
DQPC DQC DQC VDDQ VSSQ DQC DQC DQC DQC VSSQ VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSSQ DQD DQD DQD DQD VSSQ VDDQ DQD DQD DQPD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
CY7C1386D (512K X 36)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
DQPB DQB DQB VDDQ VSSQ DQB DQB DQB DQB VSSQ VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA DQA DQA VSSQ VDDQ DQA DQA DQPA
NC NC NC VDDQ VSSQ NC NC DQB DQB VSSQ VDDQ DQB DQB NC VDD NC VSS DQB DQB VDDQ VSSQ DQB DQB DQPB NC VSSQ VDDQ NC NC NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
A A CE1 CE2 NC NC BWB BWA CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
CY7C1387D (1M x 18)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
A NC NC VDDQ VSSQ NC DQPA DQA DQA VSSQ VDDQ DQA DQA VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA NC NC VSSQ VDDQ NC NC NC
MODE A A A A A1 A0 NC/72M NC/36M VSS VDD A A A A A A A A A
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
MODE A A A A A1 A0 NC/72M NC/36M VSS VDD
Document Number: 38-05545 Rev. *E
A A A A A A A A A
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Page 3 of 30
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CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F
Pin Configurations (continued) 119-Ball BGA Pinout (1 Chip Enable)
CY7C1386F (512K x 36)
1 A B C D E F G H J K L M N P R T U VDDQ NC/288M NC/144M DQC DQC VDDQ DQC DQC VDDQ DQD DQD VDDQ DQD DQD NC NC VDDQ 2 A A A DQPC DQC DQC DQC DQC VDD DQD DQD DQD DQD DQPD A NC/72M TMS 3 A A A VSS VSS VSS BWC VSS NC VSS BWD VSS VSS VSS MODE A TDI 4 ADSP ADSC VDD NC CE1 OE ADV GW VDD CLK NC BWE A1 A0 VDD A TCK 5 A A A VSS VSS VSS BWB VSS NC VSS BWA VSS VSS VSS NC A TDO 6 A A A DQPB DQB DQB DQB DQB VDD DQA DQA DQA DQA DQPA A NC/36M NC 7 VDDQ NC/576M NC/1G DQB DQB VDDQ DQB DQB VDDQ DQA DQA VDDQ DQA DQA NC ZZ VDDQ
CY7C1387F (1M x 18)
1 A B C D E F G H J K L M N P R T U VDDQ NC/288M NC/144M DQB NC VDDQ NC DQB VDDQ NC DQB VDDQ DQB NC NC NC/72M VDDQ 2 A A A NC DQB NC DQB NC VDD DQB NC DQB NC DQPB A A TMS 3 A A A VSS VSS VSS BWB VSS NC VSS NC VSS VSS VSS MODE A TDI 4 ADSP ADSC VDD NC CE1 OE ADV GW VDD CLK NC BWE A1 A0 VDD NC/36M TCK 5 A A A VSS VSS VSS NC VSS NC VSS BWA VSS VSS VSS NC A TDO 6 A A A DQPA NC DQA NC DQA VDD NC DQA NC DQA NC A A NC 7 VDDQ NC/576M NC/1G NC DQA VDDQ DQA NC VDDQ DQA NC VDDQ NC DQA NC ZZ VDDQ
Document Number: 38-05545 Rev. *E
Page 4 of 30
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CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F
Pin Configurations (continued) 165-Ball FBGA Pinout (3 Chip Enable)
CY7C1386D (512K x 36)
1 A B C D E F G H J K L M N P R
NC/288M NC/144M DQPC DQC DQC DQC DQC NC DQD DQD DQD DQD DQPD NC MODE
2
A A NC DQC DQC DQC DQC NC DQD DQD DQD DQD NC NC/72M NC/36M
3
CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A
4
BWC BWD VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS
A
5
BWB BWA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI
TMS
6
CE3 CLK
7
BWE GW VSS
8
ADSC OE
9
ADV ADSP VDDQ
10
A A NC/1G DQB DQB DQB DQB NC DQA DQA DQA DQA NC A A
11
NC NC/512M DQPB DQB DQB DQB DQB ZZ DQA DQA DQA DQA DQPA A A
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A A1 A0
VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK
VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS
A
VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A
A
A
A
CY7C1387D (1M x 18)
1 A B C D E F G H J K L M N P R
NC/288M NC/144M NC NC NC NC NC NC DQB DQB DQB DQB DQPB NC MODE
2
A A NC DQB DQB DQB DQB NC NC NC NC NC NC NC/72M NC/36M
3
CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A
4
BWB NC VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS
A
5
NC BWA VSS VSS VSS VSS VSS VSS `VSS VSS VSS VSS NC TDI
TMS
6
CE3 CLK
7
BWE GW
8
ADSC OE
9
ADV ADSP
10
A A NC/1G NC NC NC NC NC DQA DQA DQA DQA NC A A
11
A NC/576M DQPA DQA DQA DQA DQA ZZ NC NC NC NC NC A A
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A A1 A0
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK
VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS
A
VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A
A
A
A
Document Number: 38-05545 Rev. *E
Page 5 of 30
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CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F
Pin Definitions
Name A0, A1, A IO InputSynchronous InputSynchronous InputSynchronous InputSynchronous InputClock InputSynchronous InputSynchronous InputSynchronous Description Address inputs used to select one of the address locations. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 [2] are sampled active. A1: A0 are fed to the two-bit counter. Byte write select inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled on the rising edge of CLK. Global write enable input, active LOW. When asserted LOW on the rising edge of CLK, a global write is conducted (all bytes are written, regardless of the values on BWX and BWE). Byte write enable input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted LOW to conduct a byte write. Clock input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation. Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 [2] to select or deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a new external address is loaded. Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3[2] to select or deselect the device. CE2 is sampled only when a new external address is loaded. Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select or deselect the device. Not connected for BGA. Where referenced, CE3 [2] is assumed active throughout this document for BGA. CE3 is sampled only when a new external address is loaded. Output enable, asynchronous input, active LOW. Controls the direction of the IO pins. When LOW, the IO pins behave as outputs. When deasserted HIGH, DQ pins are tri-stated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state. Advance input signal, sampled on the rising edge of CLK, active LOW. When asserted, it automatically increments the address in a burst cycle. Address strobe from processor, sampled on the rising edge of CLK, active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH. Address strobe from controller, sampled on the rising edge of CLK, active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ZZ sleep input, active HIGH. When asserted HIGH places the device in a non-time critical sleep condition with data integrity preserved. For normal operation, this pin has to be LOW. ZZ pin has an internal pull down. Bidirectional data IO lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX are placed in a tri-state condition. Power supply inputs to the core of the device. Page 6 of 30
BWA, BWB BWC, BWD GW
BWE CLK CE1
CE2 [2]
CE3 [2]
OE
InputAsynchronous
ADV ADSP
InputSynchronous InputSynchronous
ADSC
InputSynchronous
ZZ
InputAsynchronous IOSynchronous
DQs, DQPX
VDD
Power Supply
Document Number: 38-05545 Rev. *E
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CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F
Pin Definitions (continued)
Name VSS VSSQ VDDQ MODE IO Ground IO Ground IO Power Supply InputStatic JTAG serial output Synchronous JTAG serial input Synchronous JTAG serial input Synchronous JTAGClock - - Ground for the IO circuitry. Power supply for the IO circuitry. Selects burst order. When tied to GND selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. This is a strap pin and must remain static during device operation. Mode pin has an internal pull up. Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG feature is not used, this pin must be disconnected. This pin is not available on TQFP packages. Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not used, this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages. Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not used, this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages. Clock input to the JTAG circuitry. If the JTAG feature is not used, this pin must be connected to VSS. This pin is not available on TQFP packages. No Connects. Not internally connected to the die These pins are not connected. They will be used for expansion to the 36M, 72M, 144M, 288M, 576M, and 1G densities. Description Ground for the core of the device.
TDO
TDI
TMS
TCK NC NC/(36M, 72M, 144M, 288M, 576M, 1G)
Functional Overview
All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The CY7C1386D/CY7C1387D/CY7C1386F/CY7C1387F supports secondary cache in systems using either a linear or interleaved burst sequence. The interleaved burst order supports Pentium(R) and i486TM processors. The linear burst sequence is suited for processors that use a linear burst sequence. The burst order is user selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the processor address strobe (ADSP) or the controller address strobe (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte write operations are qualified with the byte write enable (BWE) and byte write select (BWX) inputs. A global write enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self timed write circuitry. and an Synchronous chip selects CE1, CE2, CE3 asynchronous output enable (OE) provide for easy bank selection and output tri-state control. ADSP is ignored if CE1 is HIGH.
[2]
Single Read Accesses This access is initiated when the following conditions are satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2) chip selects are all asserted active, and (3) the write signals (GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1 is HIGH. The address presented to the address inputs is stored into the address advancement logic and the address register while being presented to the memory core. The corresponding data is allowed to propagate to the input of the output registers. At the rising edge of the next clock the data is allowed to propagate through the output register and onto the data bus within tCO if OE is active LOW. The only exception occurs when the SRAM is emerging from a deselected state to a selected state, its outputs are always tri-stated during the first cycle of the access. After the first cycle of the access, the outputs are controlled by the OE signal. Consecutive single read cycles are supported. The CY7C1386D/CY7C1387D/CY7C1386F/CY7C1387F is a double cycle deselect part. Once the SRAM is deselected at clock rise by the chip select and either ADSP or ADSC signals, its output will tri-state immediately after the next clock rise. Single Write Accesses Initiated by ADSP This access is initiated when both of the following conditions are satisfied at clock rise: (1) ADSP is asserted LOW, and (2) chip select is asserted active. The address presented is loaded into the address register and the address advancement logic while being delivered to the memory core. Page 7 of 30
Document Number: 38-05545 Rev. *E
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CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F
The write signals (GW, BWE, and BWX) and ADV inputs are ignored during this first cycle. ADSP triggered write accesses require two clock cycles to complete. If GW is asserted LOW on the second clock rise, the data presented to the DQx inputs is written into the corresponding address location in the memory core. If GW is HIGH, then the write operation is controlled by BWE and BWX signals. The CY7C1386D/CY7C1387D/CY7C1386F/CY7C1387F provides byte write capability that is described in the write cycle description table. Asserting the byte write enable input (BWE) with the selected byte write input, will selectively write to only the desired bytes. Bytes not selected during a byte write operation will remain unaltered. A synchronous self timed write mechanism has been provided to simplify the write operations. The CY7C1386D/CY7C1387D/CY7C1386F/CY7C1387F is a common IO device, the output enable (OE) must be deasserted HIGH before presenting data to the DQ inputs. Doing so will tri-state the output drivers. As a safety precaution, DQ are automatically tri-stated whenever a write cycle is detected, regardless of the state of OE. Single Write Accesses Initiated by ADSC ADSC write accesses are initiated when the following conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deasserted HIGH, (3) chip select is asserted active, and (4) the appropriate combination of the write inputs (GW, BWE, and BWX) are asserted active to conduct a write to the desired byte(s). ADSC triggered write accesses require a single clock cycle to complete. The address presented is loaded into the address register and the address advancement logic while being delivered to the memory core. The ADV input is ignored during this cycle. If a global write is conducted, the data presented to the DQX is written into the corresponding address location in the memory core. If a byte write is conducted, only the selected bytes are written. Bytes not selected during a byte write operation will remain unaltered. A synchronous self timed write mechanism has been provided to simplify the write operations. The CY7C1386D/CY7C1387D/CY7C1386F/CY7C1387F is a common IO device, the output enable (OE) must be deasserted HIGH before presenting data to the DQX inputs. Doing so will tri-state the output drivers. As a safety precaution, DQX are automatically tri-stated whenever a write cycle is detected, regardless of the state of OE. Burst Sequences The CY7C1386D/CY7C1387D/CY7C1386F/CY7C1387F provides a two-bit wraparound counter, fed by A[1:0], that implements either an interleaved or linear burst sequence. The interleaved burst sequence is designed specifically to support Intel Pentium applications. The linear burst sequence is designed to support processors that follow a linear burst sequence. The burst sequence is user selectable through the MODE input. Asserting ADV LOW at clock rise will automatically increment the burst counter to the next address in the burst sequence. Both read and write burst operations are supported. Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation sleep mode. Two clock cycles are required to enter into or exit from this sleep mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the sleep mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the sleep mode. CEs, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW.
Interleaved Burst Address Table (MODE = Floating or VDD)
First Address A1: A0 00 01 10 11 Second Address A1: A0 01 00 11 10 Third Address A1: A0 10 11 00 01 Fourth Address A1: A0 11 10 01 00
Linear Burst Address Table (MODE = GND)
First Address A1: A0 00 01 10 11 Second Address A1: A0 01 10 11 00 Third Address A1: A0 10 11 00 01 Fourth Address A1: A0 11 00 01 10
ZZ Mode Electrical Characteristics
Parameter IDDZZ tZZS tZZREC tZZI tRZZI Description Sleep mode standby current Device operation to ZZ ZZ recovery time ZZ Active to sleep current ZZ Inactive to exit sleep current Test Conditions ZZ > VDD - 0.2V ZZ > VDD - 0.2V ZZ < 0.2V This parameter is sampled This parameter is sampled 0 2tCYC 2tCYC Min Max 80 2tCYC Unit mA ns ns ns ns
Document Number: 38-05545 Rev. *E
Page 8 of 30
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CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F
Truth Table [4, 5, 6, 7, 8]
Operation Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle, Power Down Sleep Mode, Power Down Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst Add. Used None None None None None None External External External External External Next Next Next Next Next Next Current Current Current Current Current Current CE1 H L L L L X L L L L L X X H H X H X X H H X H CE2 X L X L X X H H H H H X X X X X X X X X X X X CE3 X X H X H X L L L L L X X X X X X X X X X X X ZZ L L L L L H L L L L L L L L L L L L L L L L L ADSP X L L H H X L L H H H H H X X H X H H X X H X ADSC L X X L L X X X L L L H H H H H H H H H H H H ADV X X X X X X X X X X X L L L L L L H H H H H H WRITE OE CLK X X X X X X X X L H H H H H H L L H H H H L L X X X X X X L H X L H L H L H X X L H L H X X L-H L-H L-H L-H L-H X L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H DQ Tri-State Tri-State Tri-State Tri-State Tri-State Tri-State Q Tri-State D Q Tri-State Q Tri-State Q Tri-State D D Q Tri-State Q Tri-State D D
Notes 4. X = Don't Care, H = Logic HIGH, L = Logic LOW. 5. WRITE = L when any one or more byte write enable signals, and BWE = L or GW = L. WRITE = H when all byte write enable signals, BWE, GW = H. 6. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 7. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a don't care for the remainder of the write cycle. 8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document Number: 38-05545 Rev. *E
Page 9 of 30
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CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F
Truth Table for Read/Write [6, 9]
Function (CY7C1386D/CY7C1386F) Read Read Write Byte A - (DQA and DQPA) Write Byte B - (DQB and DQPB) Write Bytes B, A Write Byte C - (DQC and DQPC) Write Bytes C, A Write Bytes C, B Write Bytes C, B, A Write Byte D - (DQD and DQPD) Write Bytes D, A Write Bytes D, B Write Bytes D, B, A Write Bytes D, C Write Bytes D, C, A Write Bytes D, C, B Write All Bytes Write All Bytes GW H H H H H H H H H H H H H H H H H L BWE H L L L L L L L L L L L L L L L L X BWD X H H H H H H H H L L L L L L L L X BWC X H H H H L L L L H H H H L L L L X BWB X H H L L H H L L H H L L H H L L X BWA X H L H L H L H L H L H L H L H L X
Truth Table for Read/Write [6, 9]
Function (CY7C1387D/CY7C1387F) Read Read Write Byte A - (DQA and DQPA) Write Byte B - (DQB and DQPB) Write All Bytes Write All Bytes GW H H H H H L BWE H L L L L X BWB X H H L L X BWA X H L H L X
Note 9. Table only lists a partial listing of the byte write combinations. Any Combination of BWX is valid Appropriate write will be done based on which byte write is active.
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IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1386D/CY7C1387D/CY7C1386F/CY7C1387F incorporates a serial boundary scan test access port (TAP). This part is fully compliant with 1149.1. The TAP operates using JEDEC-standard 3.3V or 2.5V IO logic levels. The CY7C1386D/CY7C1387D/CY7C1386F/CY7C1387F contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull up resistor. TDO can be left unconnected. Upon power up, the device will come up in a reset state which will not interfere with the operation of the device. Test Data-In (TDI) The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register. (See TAP Controller Block Diagram). Test Data-Out (TDO) The TDO output ball is used to serially clock data out from the registers. The output is active depending upon the current state of the TAP state machine. The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. (See TAP Controller State Diagram).
TAP Controller Block Diagram
0 Bypass Register
210
TAP Controller State Diagram
1 TEST-LOGIC RESET 0 0 RUN-TEST/ IDLE 1 SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT-DR 1 EXIT1-DR 0 PAUSE-DR 1 0 EXIT2-DR 1 UPDATE-DR 1 0 0 0 1 0 1 1 SELECT IR-SCAN 0 CAPTURE-IR 0 SHIFT-IR 1 EXIT1-IR 0 PAUSE-IR 1 EXIT2-IR 1 UPDATE-IR 1 0 0 1 0 1
TDI
Selection Circuitry
Instruction Register
31 30 29 . . . 2 1 0
S election Circuitr y
TDO
Identification Register
x. . . . .210
Boundary Scan Register
TCK TMS TAP CONTROLLER
Performing a TAP Reset A Reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This Reset does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power up, the TAP is reset internally to ensure that TDO comes up in a High-Z state. TAP Registers Registers are connected between the TDI and TDO balls and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI ball on the rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK. Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO balls as shown in the TAP Controller Block Diagram. Upon power up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section.
The 0 or 1 next to each state represents the value of TMS at the rising edge of TCK. Test Access Port (TAP) Test Clock (TCK) The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Test Mode Select (TMS) The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. This pin may be left unconnected if the TAP is not used. The ball is pulled up internally, resulting in a logic HIGH level.
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When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary `01' pattern to allow for fault isolation of the board-level serial test data path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between the TDI and TDO balls. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all the input and bidirectional balls on the SRAM. The boundary scan register is loaded with the contents of the RAM input and output ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO balls when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can be used to capture the contents of the input and output ring. The boundary scan order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor specific 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions on page 15. TAP Instruction Set Overview Eight different instructions are possible with the three bit instruction register. All combinations are listed in Identification Codes on page 15. Three of these instructions are listed as RESERVED and must not be used. The other five instructions are described in detail below. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO balls. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state. EXTEST The EXTEST instruction enables the preloaded data to be driven out through the system output pins. This instruction also selects the boundary scan register to be connected for serial access between the TDI and TDO in the Shift-DR controller state. IDCODE The IDCODE instruction causes a vendor specific 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO balls and allows Document Number: 38-05545 Rev. *E the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power up or whenever the TAP controller is given a test logic reset state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO balls when the TAP controller is in a Shift-DR state. The SAMPLE Z command places all SRAM outputs into a High-Z state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the input and output pins is captured in the boundary scan register. The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. As there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. To guarantee that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture setup plus hold times (tCS and tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. PRELOAD allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation. The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required; that is, while data captured is shifted out, the preloaded data can be shifted in. BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO balls. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. EXTEST Output Bus Tri-State IEEE Standard 1149.1 mandates that the TAP controller be able to put the output bus into a tri-state mode. The boundary scan register has a special bit located at bit #85 (for 119-BGA package) or bit #89 (for 165-FBGA package). When this scan cell, called the "extest output bus tri-state," is latched into the preload register during the Update-DR state in Page 12 of 30
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the TAP controller, it will directly control the state of the output (Q-bus) pins, when the EXTEST is entered as the current instruction. When HIGH, it will enable the output buffers to drive the output bus. When LOW, this bit will place the output bus into a High-Z condition. This bit can be set by entering the SAMPLE/PRELOAD or EXTEST command, and then shifting the desired bit into that cell, during the Shift-DR state. During Update-DR, the value loaded into that shift-register cell will latch into the preload register. When the EXTEST instruction is entered, this bit will directly control the output Q-bus pins. Note that this bit is preset HIGH to enable the output when the device is powered up, and also when the TAP controller is in the Test-Logic-Reset state. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions.
TAP Timing
1 Test Clock (TCK)
t TMSS
2
3
4
5
6
t TH t TMSH
t
TL
t CYC
Test Mode Select (TMS)
t TDIS t TDIH
Test Data-In (TDI)
t TDOV t TDOX
Test Data-Out (TDO) DON'T CARE UNDEFINED
TAP AC Switching Characteristics
Over the Operating Range [10, 11] Parameter Clock tTCYC tTF tTH tTL Output Times tTDOV tTDOX Set-up Times tTMSS tTDIS tCS Hold Times tTMSH tTDIH tCH TMS Hold after TCK Clock Rise TDI Hold after Clock Rise Capture Hold after Clock Rise 5 5 5 ns ns ns TMS Set-up to TCK Clock Rise TDI Set-up to TCK Clock Rise Capture Set-up to TCK Rise 5 5 5 ns ns ns TCK Clock LOW to TDO Valid TCK Clock LOW to TDO Invalid 0 10 ns ns TCK Clock Cycle Time TCK Clock Frequency TCK Clock HIGH time TCK Clock LOW time 20 20 50 20 ns MHz ns ns Description Min Max Unit
Notes 10. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register. 11. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.
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3.3V TAP AC Test Conditions
Input pulse levels .................................................VSS to 3.3V Input rise and fall times .................................................. 1 ns Input timing reference levels ...........................................1.5V Output reference levels...................................................1.5V Test load termination supply voltage...............................1.5V
2.5V TAP AC Test Conditions
Input pulse levels................................................ .VSS to 2.5V Input rise and fall time .....................................................1 ns Input timing reference levels ........................................ 1.25V Output reference levels ................................................ 1.25V Test load termination supply voltage ............................ 1.25V
3.3V TAP AC Output Load Equivalent
1.5V 50 TDO Z O= 50 20pF
2.5V TAP AC Output Load Equivalent
1.25V 50 TDO Z O= 50 20pF
TAP DC Electrical Characteristics And Operating Conditions
(0C < TA < +70C; VDD = 3.3V 0.165V unless otherwise noted) [12] Parameter VOH1 VOH2 VOL1 VOL2 VIH VIL IX Description Output HIGH Voltage Output HIGH Voltage Output LOW Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current Test Conditions IOH = -4.0 mA, VDDQ = 3.3V IOH = -1.0 mA, VDDQ = 2.5V IOH = -100 A VDDQ = 3.3V VDDQ = 2.5V IOL = 8.0 mA, VDDQ = 3.3V IOL = 8.0 mA, VDDQ = 2.5V IOL = 100 A VDDQ = 3.3V VDDQ = 2.5V VDDQ = 3.3V VDDQ = 2.5V GND < VIN < VDDQ VDDQ = 3.3V VDDQ = 2.5V 2.0 1.7 -0.5 -0.3 -5 Min 2.4 2.0 2.9 2.1 0.4 0.4 0.2 0.2 VDD + 0.3 VDD + 0.3 0.7 0.7 5 Max Unit V V V V V V V V V V V V A
Note 12. All voltages referenced to VSS (GND).
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Identification Register Definitions
Instruction Field Revision Number (31:29) Device Depth (28:24)
[13]
CY7C1386D/CY7C1386F CY7C1387D/CY7C1387F (512K x 36) (1M x 18) 000 01011 101110 000110 100101 00000110100 1 000 01011 101110 000110 010101 00000110100 1
Description Describes the version number Reserved for internal use. Defines the memory type and architecture. Defines the memory type and architecture. Defines the width and density. Allows unique identification of SRAM vendor. Indicates the presence of an ID register.
Device Width (23:18) 119-BGA Device Width (23:18) 165-FBGA Cypress Device ID (17:12) Cypress JEDEC ID Code (11:1) ID Register Presence Indicator (0)
Scan Register Sizes
Register Name Instruction Bypass ID Boundary Scan Order (119-ball BGA package) Boundary Scan Order (165-ball FBGA package) Bit Size (x18) 3 1 32 85 89 Bit Size (x36) 3 1 32 85 89
Identification Codes
Instruction EXTEST IDCODE SAMPLE Z RESERVED SAMPLE/PRELOA D RESERVED RESERVED BYPASS Code 000 001 010 011 100 101 110 111 Description Captures IO ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM outputs to High-Z state. Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operations. Captures IO ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. Do Not Use. This instruction is reserved for future use. Captures IO ring contents. Places the boundary scan register between TDI and TDO. Does not affect SRAM operation. Do Not Use. This instruction is reserved for future use. Do Not Use. This instruction is reserved for future use. Places the bypass register between TDI and TDO. This operation does not affect SRAM operations.
Note 13. Bit #24 is 1 in the register definitions for both 2.5V and 3.3V versions of this device.
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119-Ball BGA Boundary Scan Order [14, 15]
Bit # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Ball ID H4 T4 T5 T6 R5 L5 R6 U6 R7 T7 P6 N7 M6 L7 K6 P7 N6 L6 K7 J5 H6 G7 Bit # 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Ball ID F6 E7 D7 H7 G6 E6 D6 C7 B7 C6 A6 C5 B5 G5 B6 D4 B4 F4 M4 A5 K4 E4 Bit # 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 Ball ID G4 A4 G3 C3 B2 B3 A3 C2 A2 B1 C1 D2 E1 F2 G1 H2 D1 E2 G2 H1 J3 2K Bit # 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 Ball ID L1 M2 N1 P1 K1 L2 N2 P2 R3 T1 R1 T2 L3 R2 T3 L4 N4 P4 Internal
Notes 14. Balls that are NC (No Connect) are preset LOW. 15. Bit#85 is preset HIGH.
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165-Ball BGA Boundary Scan Order [14, 16]
Bit # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Ball ID N6 N7 N10 P11 P8 R8 R9 P9 P10 R10 R11 H11 N11 M11 L11 K11 J11 M10 L10 K10 J10 H9 H10 G11 F11 E11 D11 G10 F10 E10 Bit # 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Ball ID D10 C11 A11 B11 A10 B10 A9 B9 C10 A8 B8 A7 B7 B6 A6 B5 A5 A4 B4 B3 A3 A2 B2 C2 B1 A1 C1 D1 E1 F1 Bit # 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 Ball ID G1 D2 E2 F2 G2 H1 H3 J1 K1 L1 M1 J2 K2 L2 M2 N1 N2 P1 R1 R2 P3 R3 P2 R4 P4 N5 P6 R6 Internal
Note 16. Bit#89 is preset HIGH.
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Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the device. For user guidelines, not tested. Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage on VDD Relative to GND ....... -0.5V to +4.6V Supply Voltage on VDDQ Relative to GND ...... -0.5V to +VDD DC Voltage Applied to Outputs in Tri-State........................................... -0.5V to VDDQ + 0.5V DC Input Voltage ................................... -0.5V to VDD + 0.5V Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current ................................................... > 200 mA
Operating Range
Ambient VDD VDDQ Temperature Commercial 0C to +70C 3.3V -5%/+10% 2.5V - 5% to VDD Industrial -40C to +85C Range
Electrical Characteristics
Over the Operating Range [17, 18] Parameter Description VDD Power Supply Voltage VDDQ VOH VOL VIH VIL IX IO Supply Voltage Test Conditions Min 3.135 3.135 2.375 2.4 2.0 Max 3.6 VDD 2.625 Unit V V V V V V V V V V V A A A A A A mA mA mA mA mA mA mA
for 3.3V IO for 2.5V IO Output HIGH Voltage for 3.3V IO, IOH = -4.0 mA for 2.5V IO, IOH = -1.0 mA Output LOW Voltage for 3.3V IO, IOL = 8.0 mA for 2.5V IO, IOL = 1.0 mA Input HIGH Voltage [17] for 3.3V IO for 2.5V IO [17] Input LOW Voltage for 3.3V IO for 2.5V IO Input Leakage Current GND VI VDDQ except ZZ and MODE Input Current of MODE Input = VSS Input = VDD Input Current of ZZ Input = VSS Input = VDD Output Leakage Current GND VI VDDQ, Output Disabled VDD Operating Supply VDD = Max., IOUT = 0 mA, 4-ns cycle, 250 MHz Current f = fMAX = 1/tCYC 5-ns cycle, 200 MHz 6-ns cycle, 167 MHz Automatic CE VDD = Max, Device Deselected, 4-ns cycle, 250 MHz Power Down VIN VIH or VIN VIL 5-ns cycle, 200 MHz Current--TTL Inputs f = fMAX = 1/tCYC 6-ns cycle, 167 MHz Automatic CE VDD = Max, Device Deselected, All speeds Power Down VIN 0.3V or VIN > VDDQ - 0.3V, Current--CMOS Inputs f = 0 Automatic CE VDD = Max, Device Deselected, or 4-ns cycle, 250 MHz Power Down VIN 0.3V or VIN > VDDQ - 0.3V 5-ns cycle, 200 MHz Current--CMOS Inputs f = fMAX = 1/tCYC 6-ns cycle, 167 MHz Automatic CE VDD = Max, Device Deselected, All Speeds Power Down VIN VIH or VIN VIL, f = 0 Current--TTL Inputs
2.0 1.7 -0.3 -0.3 -5 -30
0.4 0.4 VDD + 0.3V VDD + 0.3V 0.8 0.7 5
5 -5 -5 30 5 350 300 275 160 150 140 70
IOZ IDD
ISB1
ISB2 ISB3
ISB4
135 130 125 80
mA mA mA mA
Notes 17. Overshoot: VIH(AC) < VDD +1.5V (pulse width less than tCYC/2), undershoot: VIL(AC) > -2V (pulse width less than tCYC/2). 18. TPower up: assumes a linear ramp from 0V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
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Capacitance [19]
Parameter CIN CCLK CIO Description Input Capacitance Clock Input Capacitance Input/Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VDD = 3.3V VDDQ = 2.5V 100 TQFP Max. 5 5 5 119 BGA Max 8 8 8 165 FBGA Max 9 9 9 Unit pF pF pF
Thermal Resistance [19]
Parameter JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with EIA/JESD51. 100 TQFP Package 28.66 4.08 119 BGA Package 23.8 6.2 165 FBGA Package 20.7 4.0 Unit C/W C/W
AC Test Loads and Waveforms
3.3V IO Test Load
OUTPUT Z0 = 50 3.3V OUTPUT RL = 50
R = 317 VDDQ 5 pF GND R = 351 10%
ALL INPUT PULSES 90% 90% 10% 1 ns
VT = 1.5V
1 ns
(a) 2.5V IO Test Load
OUTPUT Z0 = 50 2.5V
INCLUDING JIG AND SCOPE
(b)
R = 1667 VDDQ
(c)
ALL INPUT PULSES 10% 90% 90% 10% 1 ns
OUTPUT RL = 50 VT = 1.25V
5 pF
GND R = 1538
1 ns
(a)
INCLUDING JIG AND SCOPE
(b)
(c)
Note 19. Tested initially and after any design or process change that may affect these parameters.
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Switching Characteristics Over the Operating Range [20, 21]
Parameter tPOWER Clock tCYC tCH tCL Output Times tCO tDOH tCLZ tCHZ tOEV tOELZ tOEHZ Set-up Times tAS tADS tADVS tWES tDS tCES Hold Times tAH tADH tADVH tWEH tDH tCEH Address Hold After CLK Rise ADSP, ADSC Hold After CLK Rise ADV Hold After CLK Rise GW, BWE, BWX Hold After CLK Rise Data Input Hold After CLK Rise Chip Enable Hold After CLK Rise 0.3 0.3 0.3 0.3 0.3 0.3 0.4 0.4 0.4 0.4 0.4 0.4 0.5 0.5 0.5 0.5 0.5 0.5 ns ns ns ns ns ns Address Set-up Before CLK Rise ADSC, ADSP Set-up Before CLK Rise ADV Set-up Before CLK Rise GW, BWE, BWX Set-up Before CLK Rise Data Input Set-up Before CLK Rise Chip Enable Set-Up Before CLK Rise 1.2 1.2 1.2 1.2 1.2 1.2 1.4 1.4 1.4 1.4 1.4 1.4 1.5 1.5 1.5 1.5 1.5 1.5 ns ns ns ns ns ns Data Output Valid after CLK Rise Data Output Hold after CLK Rise Clock to Low-Z [23, 24, 25] Clock to High-Z [23, 24, 25] OE LOW to Output Valid OE LOW to Output Low-Z [23, 24, 25] OE HIGH to Output High-Z [23, 24, 25] 0 2.6 1.0 1.0 2.6 2.6 0 3.0 2.6 1.3 1.3 3.0 3.0 0 3.4 3.0 1.3 1.3 3.4 3.4 3.4 ns ns ns ns ns ns ns Clock Cycle Time Clock HIGH Clock LOW 4.0 1.7 1.7 5.0 2.0 2.0 6.0 2.2 2.2 ns ns ns Description VDD(Typical) to the First Access [22] -250 Min 1 Max Min 1 -200 Max 1 -167 Min Max Unit ms
Notes 20. Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V. 21. Test conditions shown in (a) of AC Test Loads unless otherwise noted. 22. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation can be initiated. 23. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured 200 mV from steady-state voltage. 24. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions. 25. This parameter is sampled and not 100% tested.
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Switching Waveforms
Read Cycle Timing [26]
tCYC
CLK
tCH t ADS tADH tCL
ADSP
t ADS tADH
ADSC
t AS tAH
ADDRESS
A1
t WES tWEH
A2
A3 Burst continued with new base address
GW, BWE,BW
X t CES tCEH
Deselect cycle
CE
t ADVS tADVH
ADV ADV suspends burst OE
t OEV t CLZ t OEHZ t OELZ t CO t DOH t CHZ
Data Out (DQ)
High-Z
Q(A1)
t CO
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A3)
Single READ
BURST READ
Burst wraps around to its initial state
DON'T CARE
UNDEFINED
Note 26. On this diagram, when CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
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Switching Waveforms (continued)
Write Cycle Timing [26, 27]
t CYC
CLK
tCH t ADS tADH tCL
ADSP
t ADS tADH
ADSC extends burst
t ADS tADH
ADSC
t AS tAH
ADDRESS
A1
A2
Byte write signals are ignored for first cycle when ADSP initiates burst
A3
t WES tWEH
BWE, BW X
t WES tWEH
GW
t CES tCEH
CE
t ADVS tADVH
ADV
ADV suspends burst
OE
t DS t DH
Data in (D)
High-Z
t OEHZ
D(A1)
D(A2)
D(A2 + 1)
D(A2 + 3)
D(A3)
D(A3 + 1)
Data Out (Q)
BURST READ
Single WRITE DON'T CARE
BURST WRITE UNDEFINED
Extended BURST WRITE
Note 27. Full width write can be initiated by either GW LOW, or by GW HIGH, BWE LOW, and BWX LOW.
Document Number: 38-05545 Rev. *E
Page 22 of 30
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CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F
Switching Waveforms (continued)
Read/Write Cycle Timing [26, 28, 29]
t CYC
CLK
tCH t ADS tADH tCL
ADSP
ADSC
t AS tAH
ADDRESS BWE, BW
X
A1
A2
A3
t WES tWEH
A4
A5
A6
t CES
tCEH
CE
ADV
OE
tCO t DS tDH t OELZ
Data In (D) Data Out (Q)
High-Z
tCLZ
tOEHZ
D(A3)
D(A5)
D(A6)
High-Z
Q(A1) Back-to-Back READs
Q(A2) Single WRITE DON'T CARE
Q(A4) BURST READ UNDEFINED
Q(A4+3) Back-to-Back WRITEs
Notes 28. The data bus (Q) remains in high-Z following a Write cycle, unless a new read access is initiated by ADSP or ADSC. 29. GW is HIGH.
Document Number: 38-05545 Rev. *E
Page 23 of 30
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CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F
Switching Waveforms (continued)
ZZ Mode Timing [30, 31]
CLK
t ZZ t ZZREC
ZZ
t
ZZI
I
SUPPLY I DDZZ t RZZI DESELECT or READ Only
ALL INPUTS (except ZZ)
Outputs (Q)
High-Z
DON'T CARE
Notes 30. Device must be deselected when entering ZZ sleep mode. See cycle descriptions table for all possible signal conditions to deselect the device. 31. DQs are in high-Z when exiting ZZ sleep mode.
Document Number: 38-05545 Rev. *E
Page 24 of 30
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CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F
Ordering Information
Not all of the speed, package, and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) 167 Ordering Code CY7C1386D-167AXC CY7C1387D-167AXC CY7C1386F-167BGC CY7C1387F-167BGC CY7C1386F-167BGXC CY7C1387F-167BGXC CY7C1386D-167BZC CY7C1387D-167BZC CY7C1386D-167BZXC CY7C1387D-167BZXC CY7C1386D-167AXI CY7C1387D-167AXI CY7C1386F-167BGI CY7C1387F-167BGI CY7C1386F-167BGXI CY7C1387F-167BGXI CY7C1386D-167BZI CY7C1387D-167BZI CY7C1386D-167BZXI CY7C1387D-167BZXI 200 CY7C1386D-200AXC CY7C1387D-200AXC CY7C1386F-200BGC CY7C1387F-200BGC CY7C1386F-200BGXC CY7C1387F-200BGXC CY7C1386D-200BZC CY7C1387D-200BZC CY7C1386D-200BZXC CY7C1387D-200BZXC CY7C1386D-200AXI CY7C1387D-200AXI CY7C1386F-200BGI CY7C1387F-200BGI CY7C1386F-200BGXI CY7C1387F-200BGXI CY7C1386D-200BZI CY7C1387D-200BZI CY7C1386D-200BZXI CY7C1387D-200BZXI 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free Industrial 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free Commercial 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free Industrial 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Package Diagram Part and Package Type Operating Range Commercial
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
Document Number: 38-05545 Rev. *E
Page 25 of 30
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CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F
Ordering Information (continued)
Not all of the speed, package, and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. 250 CY7C1386D-250AXC CY7C1387D-250AXC CY7C1386F-250BGC CY7C1387F-250BGC CY7C1386F-250BGXC CY7C1387F-250BGXC CY7C1386D-250BZC CY7C1387D-250BZC CY7C1386D-250BZXC CY7C1387D-250BZXC CY7C1386D-250AXI CY7C1387D-250AXI CY7C1386F-250BGI CY7C1387F-250BGI CY7C1386F-250BGXI CY7C1387F-250BGXI CY7C1386D-250BZI CY7C1387D-250BZI CY7C1386D-250BZXI CY7C1387D-250BZXI 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free Industrial 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free Commercial
Document Number: 38-05545 Rev. *E
Page 26 of 30
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CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F
Package Diagrams
Figure 1. 100-Pin Thin Plastic Quad Flat pack (14 x 20 x 1.4 mm) (51-85050)
16.000.20 14.000.10
100 1 81 80
1.400.05
0.300.08
22.000.20
20.000.10
0.65 TYP.
30 31 50 51
121 (8X)
SEE DETAIL
A
0.20 MAX. 1.60 MAX. 0 MIN. SEATING PLANE 0.25 GAUGE PLANE STAND-OFF 0.05 MIN. 0.15 MAX.
NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3. DIMENSIONS IN MILLIMETERS
0-7
R 0.08 MIN. 0.20 MAX.
0.600.15 0.20 MIN. 1.00 REF.
DETAIL
51-85050-*B
A
Document Number: 38-05545 Rev. *E
0.10
R 0.08 MIN. 0.20 MAX.
Page 27 of 30
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CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F
Package Diagrams (continued)
Figure 2. 119-Ball BGA (14 x 22 x 2.4 mm) (51-85115)
51-85115-*B
Document Number: 38-05545 Rev. *E
Page 28 of 30
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CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F
Package Diagrams (continued)
Figure 3. 165-Ball FBGA (13 x 15 x 1.4 mm) (51-85180)
BOTTOM VIEW TOP VIEW TOP VIEW PIN 1 CORNER PIN 1 CORNER
1 A B C D E F G 2 3 4 5 6 7 8 9 10 11 11 10 9 8 7
PIN BOTTOM VIEW 1 CORNER PIN 1 CORNER O0.05 M C O0.25 MO0.05 M C CAB O0.25 O0.50 -0.06 (165X) M C A B
+0.14 4 6 5
O0.50 -0.06 (165X)
3 +0.14 2 1
1 A B
2
3
4
5
6
7
8
9
10
11
11
10
9
8
7
6
5
4
3
2
1A
B
A B C D E F G H J K L M N P R
D E F
1.00
C
1.00
C D E F G
15.000.10
15.000.10
15.000.10
H J K L M N P R
G H J K
14.00 15.000.10
H
14.00
J K
M N P R
7.00
L
7.00
L M N P R
A A
A A 5.00 5.00 10.00 10.00 B B 13.000.10 13.000.10 0.15(4X) B B 13.000.10
1.00 1.00
13.000.10
1.40 MAX.
0.530.05 0.25 C
0.15(4X)
SEATING PLANE 0.36 C 0.36 C SEATING PLANE 0.350.06
NOTES : NOTES : SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD) PACKAGE WEIGHT : 0.475gNON-SOLDER MASK DEFINED (NSMD) SOLDER PAD TYPE : JEDEC REFERENCE : MO-216 / DESIGN 4.6C PACKAGE WEIGHT : 0.475g PACKAGE CODE : BB0AC : MO-216 / DESIGN 4.6C JEDEC REFERENCE PACKAGE CODE : BB0AC
51-85180-*A
0.25 C
1.40 MAX.
0.530.05
0.15 C
0.15 C
Intel and Pentium are registered trademarks, and i486 is a trademark of Intel Corporation. PowerPC is a trademark of IBM Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.
Document Number: 38-05545 Rev. *E
0.350.06
51-85180-*A
Page 29 of 30
(c) Cypress Semiconductor Corporation, 2006-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F
Document History Page
Document Title: CY7C1386D/CY7C1387D/CY7C1386F/CY7C1387F, 18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM Document Number: 38-05545 REV. ** *A ECN NO. 254550 288531 Issue Date See ECN See ECN Orig. of Change RKF SYT New data sheet Edited description under "IEEE 1149.1 Serial Boundary Scan (JTAG)" for non-compliance with 1149.1 Removed 225Mhz Speed Bin Added Pb-free information for 100-pin TQFP, 119 BGA and 165 FBGA Packages. Added comment of `Pb-free BG packages availability' below the Ordering Information Address expansion pins/balls in the pinouts for all packages are modified as per JEDEC standard Added description on EXTEST Output Bus Tri-State Changed description on the Tap Instruction Set Overview and Extest Changed Device Width (23:18) for 119-BGA from 000110 to 101110 Added separate row for 165 -FBGA Device Width (23:18) Changed JA and JC for TQFP Package from 31 and 6 C/W to 28.66 and 4.08 C/W respectively Changed JA and JC for BGA Package from 45 and 7 C/W to 23.8 and 6.2 C/W respectively Changed JA and JC for FBGA Package from 46 and 3 C/W to 20.7 and 4.0 C/W respectively Modified VOL, VOH test conditions Removed comment of `Pb-free BG packages availability' below the Ordering Information Updated Ordering Information Table Converted from Preliminary to Final. Changed address of Cypress Semiconductor Corporation on Page# 1 from "3901 North First Street" to "198 Champion Court" Changed the description of IX from Input Load Current to Input Leakage Current on page# 18. Changed the IX current values of MODE on page # 18 from -5 A and 30 A to -30 A and 5 A. Changed the IX current values of ZZ on page # 18 from -30 A and 5 A to -5 A and 30 A. Changed VIH < VDD to VIH < VDDon page # 18. Replaced Package Name column with Package Diagram in the Ordering Information table. Updated Ordering Information Table. Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP AC Switching Characteristics table. Updated the Ordering Information table. Added Part numbers CY7C1386F and CY7C1387F Added footnote# 3 regarding Chip Enable Updated Ordering Information table Description of Change
*B
326078
See ECN
PCI
*C
418125
See ECN
NXR
*D
475009
See ECN
VKN
*E
793579
See ECN
VKN
Document Number: 38-05545 Rev. *E
Page 30 of 30
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